Zigzag_scanning.jpg' alt='Serial Port Communication Matlab Codes' title='Serial Port Communication Matlab Codes' />I2. C Communication with PIC Microcontroller. I2. C or IIC or I2. C stands for Inter Integrated Circuit. It is a very popular multi master, multi slave serial communication interface developed by Philips. I2. C uses two bidirectional open drain data lines, Serial Data SDA and Serial Clock SCL with pull up resistors as shown below. Unlike UART, you can connect and communicate to multiple devices using the same I2. C bus. I2. C Communication. B15k1M/0.jpg' alt='Serial Port Communication Matlab Codes' title='Serial Port Communication Matlab Codes' />I2. C is a master slave protocol. It means that devices connected to I2. C bus will be either master or slave. The master is the device which initiate communication and it drives clock SCL line. Slaves are the devices which responds to master and it cannot initiate a communication. An I2. C bus can have multiple masters and multiple slaves. But commonly we are using single master and multiple slaves. International Journal of Engineering Research and Applications IJERA is an open access online peer reviewed international journal that publishes research. LinearLabTools is a collection of Matlab and Python programs that provide direct access to Linear Technologys data converter evaluation boards. El Abogado Del Lincoln Pdf. What are Null Pointer Exceptions java. NullPointerException and what causes them What methodstools can be used to determine the cause so that you stop the. Each slaves are identified or addressed by a unique address. The master will send address of slave RW bit first, then followed by other data. So the slave with that particular address will be activated at that moment. JtPwnmrgM/hqdefault.jpg' alt='Serial Port Communication Matlab Codes' title='Serial Port Communication Matlab Codes' />RW bit indicates whether the master wants to read data from or write data to the slave. For example, we can have a microcontroller or host device which is connected to different slave devices like IO Port Expanders, LEDLCD Drivers, ADCs, DACs, EEPROMs, Real Time Clock RTC etc. Most of the PIC microcontrollers have built in Master Synchronous Serial Port MSSP module which can be configured to operate in following modes. Serial Peripheral Interface SPIInter Integrated Circuit I2. C Slave, Master Multi master modes. In this tutorial we will learn how to operate MSSP module of PIC Microcontroller as I2. C master or slave. For demonstration we are using PIC 1. F8. 77. A microcontroller. You can easily convert it for other microcontrollers if you understand it clearly. MSSP Module in I2. C Mode. Lets see in detail about working of MSSP module of PIC Microcontroller in IC mode. MSSP module can be configured to operate in both 1. In this example we are demonstrating 7 bit mode only as it is the commonly used one. You can easily modify the program to work in 1. I2. C Master. We need to write to SSPCON1 and SSPADD registers to configure MSSP module as IC Master and to set the clock frequency of IC communication respectively. I2. C Master Block Diagram PIC Microcontroller. I2. C Slave. Similar to above, we need to write to SSPCON1 and SSPADD registers to configure MSSP module in IC slave mode and to set the slave device address respectively. I2. C Slave Block Diagram PIC Microcontroller. Clock generated by the master on SCL line will cause the data to shift in and shift out of the SSPSR register which makes the I2. C communication happen. I2. C Registers. SSPSTAT MSSP Status Register. SSPSTAT Register MSSP Module PIC 1. F8. 77. ABit 0 BF This is the Buffer Full status bit. In the transmit mode this bit will set when we write data to SSPBUF register and it is cleared when the data is shifted out. In the receive mode this bit will set when the data or address is received in the SSPBUF register and it is cleared when we reads the SSPBUF register. Bit 1 UA This is the Update Address bit and is used only in 1. It indicates that user needs to update the address in the SSPADD register. Bit 2 RW This is the ReadWrite bit information. In the slave mode it indicates the status of RW bit during the last address match. In the master mode, 1 indicates that transmit is in progress and vice versa. Bit 3 S  This bit indicates that a Start bit is detected last and it will automatically cleared during Reset. Bit 4 P As above, this bit indicates that a Stop bit is detected last and it will automatically cleared during Reset. Bit 5 DA This is the data or address indicator bit and it is used only in slave mode. If it is set, the last byte received was data otherwise it will be address. Bit 6 CKE Setting this bit enables SMBus specific inputs. SMBus is an another bus similar to I2. C, which are compatible each other. Bit 7 SMP Setting this bit disables slew rate control and vice versa. SSPCON1 MSSP Control Register 1. SSPCON1 Register MSSP Module PIC 1. F8. 77. ABit 0 3 SSPM0 SSPM3 These are synchronous serial port mode select bits. Synchronous Serial Port Mode Select bits PIC 1. F8. 77. ABit 4  CKP This is SCL clock release control bit. It is used only in slave mode. Setting this bit releases the clock. If zero, it holds the clock clock stretch. Bit 5  SSPEN  This is the synchronous serial port enable bit. Setting this bit enables the serial port. Bit 6  SSPOV This is receive over flow indicator bit. If this bit is set during receive mode, it indicates that a byte is received while SSPBUF is holding the previous value. And it has no application in transmit mode. We must clear this bit in software. Bit 7 WCOL It is the write collision detect bit. If this bit is set during master transmit mode, it indicates that a write to SSPBUF register was attempted when I2. C conditions was not valid for a transmission to be started. And if it is set during a slave transmit mode, it indicates that SSPBUF register is written when it is transmitting the previous word. We must clear this bit in software. SSPCON2 MSSP Control Register 2. SSPCON2 MSSP Module PIC 1. F8. 77. ABit 0 SEN Start Condition or Stretch Enable bit. In master mode, setting this bit initiate start condition on SCL SDA pins and it will be automatically cleared by the hardware. And in slave mode setting this bit enables clock stretching for both slave receive and slave transmit. If it is cleared in slave mode, clock stretching is enabled only for slave transmit. Bit 1 RSEN Repeated start condition enable bit. This bit has application only in master mode. Setting this bit will initiate repeated start condition on both SCL  SDA pins and it will automatically cleared in hardware. Bit 2 PEN Stop condition enable bit. This bit has application only in master mode. Setting this bit will initiate stop condition on both SCL SDA pins and it will be automatically cleared in hardware. Bit 3 RCEN Receive enable bit. This bit also has application only in master mode. Setting this bit enables receive mode for I2. C. Bit 4 ACKEN Acknowledge sequence enable bit. Setting this bit initiates acknowledge sequence on SCL SDA lines and it will send ACKDT see below bit. This bit will be automatically cleared in hardware. It has application only in master receive mode. Bit 5 ACKDT Acknowledge data bit. This value will be transmitted when we set the ACKEN bit above. This bit has application only in master receive mode. Bit 6 ACKSTAT Acknowledge status bit. This bit has application in master transmit mode only. Bit 7 GCEN General call enable bit. Setting this bit enables interrupt when a general call address is received in the register SSPSR. I2. C Library for MPLAB XC8. Master Functions. Initialize I2. C Module as Mastervoid I2. CMasterInitconst unsigned long c. SSPCON 0b. 00. 10. SSP Module as Master. SSPADD XTALFREQ4c 1 Setting Clock Speed. TRISC3 1 Setting as input as given in datasheet. TRISC4 1 Setting as input as given in datasheet. For Waitingvoid I2. CMasterWait. while SSPSTAT 0x. SSPCON2 0x. F Transmit is in progress. Start Conditionvoid I2. CMasterStart. I2. CMasterWait. SEN 1 Initiate start condition. Repeated Startvoid I2. CMasterRepeated. Start.